Digital-to-analog converters (D/A converters) are always used when, as input signals, digital numerical values, which are stored in a storage module, for example, must be converted into a (quasi) analog voltage, as output signal. In this context, the output signal, and thus an output voltage Ua, is proportional to the product of a digital input signal d and a reference voltage Uref.
                              U          a                =                              U            ref                    ⁢                                    ∑                              i                =                0                                            N                -                1                                      ⁢                                                  ⁢                                          d                i                            ⁢                              2                i                                                                        (        1        )            
Accordingly, a converter, designed as an analog-to-digital converter (A/D converter), can convert an analog input voltage, as input signal, into a digital output signal.
However, in the case of D/A converters, as well as A/D converters, errors can occur during operation that should be identified in order to improve the operational reliability of such a converter.
A method for detecting errors in a plurality of A/D converters or D/A converters is described in U.S. Pat. No. 5,583,502. The method can be implemented using a circuit that has a coincidence detecting circuit, that is designed to process output signals of the converters in order to provide a conformance test signal. Moreover, the circuit has an output unit controlled by the coincidence circuit that is designed to provide a result of a test performed for the converter. Here, however, a plurality of converters are required for one test, necessitating a relatively substantial outlay for hardware.
“Test Generation and Concurrent Error Detection in Current-Mode A/D Converters” IEEE, 1995, by Wey, Chin-Long, Shoba Krishnan and Sondes Sahli, describes using an alternating logic to protect an A/D converter. In this case, current It1=Iin to be measured is first digitized; the result is stored in a register; and current It2=Iref−Iin is converted in the next step. The two thus obtained digital values are subsequently compared to one another. In the error-free case, the second value is a complement of the first value. This method is based on time redundancy, i.e., the clock cycle of the A/D converter must be greater than or equal to twice the conversion time, so that two conversions can be performed during one clock period. However, this condition cannot be met for every application.
“A Proposal for Error Tolerating Codes” IEEE, 1993 by Matsubara, Takashi and Yoshiaki Koga describes using error-tolerant codes for A/D converters. Here, window comparators are used, which supply a logical one when the analog input voltage resides within a certain range. For every bit produced by the A/D converter, a window comparator is used, the individual comparators having different voltage ranges. Thus, the outputs of the window comparators can realize an error-tolerant code. However, this method does not provide a 100% fault coverage.